Vertical depletion mode field effect transistors (FETs) offer a more compact use of a substrate because their drain, gate, and source regions are disposed vertically above one another. Because the channels defined by such vertical FETs are necessarily much shorter than those which can be achieved in a laterally constructed FET, vertical FETs break down at relatively low drain-to-source voltages. These relatively low breakdown voltages mean that vertical FETs are not acceptable as power transistors over a full range of drain-to-source voltages.
Thus, it is desirable to create a vertical insulated gate FET (IGFET) structure which is capable of sustaining higher drain-to-source voltages than presentday vertical IGFETs.